Generally, silicidation is a process used in the fabrication of semiconductor devices to alter the composition of certain components with the aim of improving device performance. Semiconductor devices are small electrical components that are fabricated in part out of a semiconductor material such as silicon. Manufacturing electrical components in this manner permits them to be made in a very small size. For example, more than one million transistors may be fabricated on a single thin piece of silicon that is roughly square in shape and less than one inch on each side. The various electrical components fabricated on this single piece of silicon may be connected together by very small conductive elements in order to create integrated circuits. Modem integrated circuits are used in many applications, including the manufacture of computers, mobile telephones, and personal electronic gaming devices.
Most semiconductor devices are too small to be seen with the naked eye. Special fabrication techniques are therefore required for their manufacture. In general, fabrication begins with a thin slice of material, such as silicon, that is used as a substrate on which the various devices can be manufactured. This substrate material is typically formed as a solid ingot, which is then sliced into thin sections called wafers. A single wafer may be used to create over one hundred individual dice, which after fabrication are separated and separately-packaged for use in a particular electrical appliance.
Fabrication techniques may vary, but generally speaking, fabrication involves the sequential formation of layers of different conducting and insulating materials. Portions of each layer may be selectively removed to create small surface structures prior to the formation of the next layer. To accomplish this selective removal, a technique called photolithography may be used. This technique involves the formation of a layer of material referred to as photoresist, which is then selectively exposed to a light energy source that causes the exposed (or, alternately, unexposed) portions of the photoresist layer to change physical properties. A solvent is then used to remove the selected portions, leaving a pattern of structures on the surface that may be used for selective deposition or etching away of the underlying material. The remaining photoresist is removed when it is no longer required, and does not form part of the actual device. Other techniques may be used to similar effect as well.
The electrical appliances mentioned above have become very popular with consumers, in part because of their small size and consequent portability. With their popularity, however, have come demands from the marketplace for even smaller devices that are even more capable. To accomplish this, the tiny semiconductor devices formed in the fabrication process must become even smaller and more tightly packed together. This effort results not only in greater challenges during the fabrication process itself, but gives rise to certain electrical problems, such as current leakage, that detrimentally effect of the performance of the device.
One common semiconductor device is called the transistor. A transistor is a small switch that can control the flow of electricity without the need for any moving parts. One such transistor shown in FIG. 1. FIG. 1 is an elevation (side) view illustrating in cross-section an exemplary transistor 10. Transistor 10 includes a gate structure 11 formed on substrate 12. Gate structure 11 is made up of a number of different component parts. A thin layer of dielectric material, such as an oxide, separates gate electrode 14 from substrate 12. This separating layer may be referred to as gate dialectic 13. Gate electrode 14 is made of a conducting material, for example a metal. More recently, crystalline polysilicon, or simply poly, has been used instead of metal. Disposed above gate electrode 14 in this example is a contact 15, typically made of metal, which may for example be used to make reliable electrical connections between gate electrode 14 and an interconnect coupled to another device (not shown). Spacers 16 and 17, formed of a dielectric material, are disposed on either side of the gate structure 11.
Gate structure 11 is the portion of transistor 10 that controls the flow of electricity. The current itself flows through the substrate between source 18 and drain 19 through channel 20 when a small voltage is applied to the gate structure 11. Source 18 and drain 19 are each formed in the substrate 12 by a local implantation of ions, such as those of boron or phosphorus. This process of ion implantation is sometimes known as doping. Source 18 and drain 19 are in turn connected, for example, to a voltage source and to a ground (not shown), respectively. Metal contacts 21 and 22, disposed on, respectively, source 18 and drain 19, provide a site for terminating such external electrical connections. The process for making a transistor such as transistor 10 will now be briefly explained, with reference to FIG. 2.
FIG. 2 is a flow diagram illustrating an exemplary method 30 of fabricating a semiconductor device, in this case the transistor 10 shown in FIG. 1. At START 17 is assumed that all materials and equipment necessary for performing the method are available and operational. The method begins with forming an oxide layer on a substrate (step 32). A poly layer for the gate electrode is then formed (step 34) as well. A photoresist layer is then formed (step 36) and patterned (step 38) so that a photoresist structure protects the region where the gate structure will be formed. An etching step is then performed (step 40), leaving a gate structure disposed on the substrate. The remaining photoresist may then be removed (step 42). The source region and the drain region may now be partially formed by ion implantation (step 44), which as mentioned above is sometimes called doping. In many cases additional temporary or permanent protective structures must be added and removed as part of the doping process, but these steps are not shown individually. The source and drain regions are said to be partially formed because, in this example, additional ion implantation into these regions will occur later. In an alternate embodiment (not shown), the complete ion implantation is performed at this time.
In this exemplary method, a dielectric layer is then deposited (step 46) and selectively etched (step 48) to form the spacers for the gate structure. An additional ion implantation (step 50) forms the deeper part of the source region and drain region (see FIG. 1) according to the process of this example. An electrical contact region may then be formed on top of the gate electrode at this time (step 52), although the individual steps that may be involved are not separately shown in FIG. 2. At this point a transistor such as the transistor 10 of FIG. 1 has been formed and fabrication may continue with the deposition of additional material layers and the formation of additional devices.
Although, as mentioned above, the gate electrode is often formed of a poly material, it has been found advantageous to enhance the properties of the poly gate by using it to create an alloy with a metal in a process known as silicidation. In this process, generally speaking, a metal layer is deposited on top of an existing poly gate and induced to combine with the poly material in a rapid heating process often referred to as an RTA (rapid thermal anneal). One example of this process, as currently performed, is illustrated in FIG. 3. FIG. 3 is a flow diagram illustrating an exemplary fabrication method 60. The method 60 begins with forming a gate structure on the substrate (step 62), for example using a process similar to that described above in reference to steps 32 through 40 of FIG. 2. At this point, the gate electrode includes only a poly material.
A metal layer, for example of nickel, is then formed (step 64) over the gate structure. Once the metal layer is in place, a first RTA is performed (step 66), rapidly heating the deposited metal for a short period of time. This drives some of the metal into combination with the poly in the gate electrode, forming a silicide material out of at least the top portion of it. The excess metal, that is the metal material that has not combined with the poly gate, is then removed (step 68). A second RTA is then performed (step 70), to drive the metal in the poly gate further into the poly material. In contrast to previous techniques, which involved the formation of a silicide layer at the top of the poly gate, for example to create a better contact region, the first and second RTA sequences described above are intended to produce what is referred to as a FUSI (fully- silicided) gate. Note that FIG. 3 illustrates only the silicidation process; from there, fabrication continues through the additional operations involved in completing the device.
Unfortunately, problems may arise when forming silicided gates in this manner, especially when they are part of dual-gate semiconductor devices such those in CMOS applications. This is due to the fact that the different transistors in a CMOS device require for optimum performance different types, or phases, of the nickel silicon (or other) alloy that will make up the FUSI gate. Specifically, in a PMOS gate having an Ni3Si gate, an excess of the alloy will frequently occur, that is, there will be a large volume change resulting from the silicidation process. This volume change may in fact be of such magnitude as to cause damage to the underlying gate dielectric layer, which may adversely affect device performance and overall reliability.
Needed, then, is an efficient way to fabricate gates, and specifically the gate electrodes used in semiconductor devices such as transistors that can take advantage of the benefits of salicidation while at the same time minimizing, or altogether avoiding the stress-induced damage caused by volume change during salicidation. The present invention provides just such a solution.